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                            Latch up 是指[cmos](https://baike.baidu.com/item/cmos)晶片中，在電源power VDD和[地線](https://baike.baidu.com/item/%E5%9C%B0%E7%BA%BF/9752703)GND(VSS)之間由于寄生的[PNP](https://baike.baidu.com/item/PNP)和NPN雙極性BJT相互影響而產生的一低阻抗通路。它的存在會使VDD和GND之間產生大電流。

隨著IC制造工藝的發展, 封裝密度和集成度越來越高,產生Latch up的可能性會越來越大。

Latch up 產生的過度電流量可能會使芯片產生永久性的破壞, Latch up 的防范是IC Layout 的最重要措施之一


                    
                
        
                
            
        
                
    
                
    
                
        
                
    
                

                







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