7.1 溫濕度傳感器DHT11的verilog驅動 · FPGA使用筆記

` `DHT11數字溫[濕度傳感器](http://www.hqchip.com/app/42)是一款含有已校準數字信號輸出的溫濕度復合[傳感器](http://www.hqchip.com/app/835)。它應用專用的數字模塊采集技術和溫濕度傳感技術，確保產品具有極高的可靠性與卓越的長期穩定性。傳感器包括一個[電阻](http://www.hqchip.com/app/dianzudianrongdiangan)式感濕元件和一個NTC測溫元件，并與一個高性能8位[單片機](http://www.elecfans.com/tags/%E5%8D%95%E7%89%87%E6%9C%BA/)相連接。因此該產品具有品質卓越、超快響應、抗干擾能力強、性價比極高等優點。每個DHT11傳感器都在極為精確的濕度校驗室中進行校準。校準系數以程序的形式儲存在OTP內存中，傳感器內部在檢測信號的處理過程中要調用這些校準系數。單線制串行[接口](http://www.hqchip.com/app/1039)，使系統集成變得簡易快捷。超小的體積、極低的功耗，信號傳輸距離可達20米以上，使其成為各類應用甚至最為苛刻的應用場合的最佳選則。產品為4針單排引腳封裝。連接方便，特殊封裝形式可根據用戶需求而提供。 ![](https://img.kancloud.cn/3f/b2/3fb2f3fe98c7f253accbc96946f445bf_470x358.png) ![](https://img.kancloud.cn/56/1a/561ad1053c94ffc2350fafb11cdbda15_1053x536.png) ` `DHT11的供電電壓為 3－5.5V。傳感器上電后，要等待 1s 以越過不穩定狀態在此期間無需發送任何指令。電源引腳（VDD，GND）之間可增加一個100nF 的電容，用以去耦濾波。 ` `DATA 用于微處理器與 DHT11之間的通訊和同步,采用單總線數據格式,一次通訊時間4ms左右,數據分小數部分和整數部分,具體格式在下面說明,當前小數 ` `部分用于以后擴展,現讀出為零.操作流程如下: 一次完整的數據傳輸為40bit,高位先出。數據格式:8bit濕度整數數據+8bit濕度小數數據 +8bi溫度整數數據+8bit溫度小數數據 +8bit校驗和 ![](https://img.kancloud.cn/c6/5b/c65b10934a590ed1655c5aeab9f20280_1250x543.png) ![](https://img.kancloud.cn/20/e3/20e337884645187e95b8de5a3288fa9c_1117x667.png) ![](https://img.kancloud.cn/48/bb/48bb77b41efc5e72dff6046c0f55f2fa_1132x618.png) ![](https://img.kancloud.cn/ef/c3/efc396eeedefd80d62e366fd21d3e684_1094x518.png) ## verilog驅動 ``` module DHT11( input wire clk , //1MHz時鐘 input wire start ,//上升沿觸發采集 input wire rst_n , inout dat_io , output reg [39:0] data , output error ,//數據度錯誤時為1 output done//完成一次轉換后數據更新 ); wire din;//讀取的數據 reg read_flag; reg dout; reg[3:0] state; localparam s1 = 0; localparam s2 = 1; localparam s3 = 2; localparam s4 = 3; localparam s5 = 4; localparam s6 = 5; localparam s7 = 6; localparam s8 = 7; localparam s9 = 8; localparam s10 = 9; assign dat_io = read_flag ? 1'bz : dout; assign din = dat_io; assign done = (state == s10)?1'b1:1'b0; assign error = (data[7:0] == data[15:8] + data[23:16] + data[31:24] + data[39:32])?1'b0:1'b1; reg [5:0]data_cnt; reg start_f1,start_f2,start_rising; always@(posedge clk) begin if(!rst_n)begin start_f1 <=1'b0; start_f2 <= 1'b0; start_rising<= 1'b0; end else begin start_f1 <= start; start_f2 <= start_f1; start_rising <= start_f1 & (~start_f2); end end reg [39:0] data_buf; reg [15:0]cnt ; always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0)begin read_flag <= 1'b1; state <= s1; dout <= 1'b1; data_buf <= 40'd0; cnt <= 16'd0; data_cnt <= 6'd0; data<=40'd0; end else begin case(state) s1:begin//當數據總線空閑時，收到數據采集時開啟采集 if(start_rising && din==1'b1)begin state <= s2; read_flag <= 1'b0;//主機獲取總線 dout <= 1'b0;//拉低 cnt <= 16'd0; data_cnt <= 6'd0; end else begin read_flag <= 1'b1; dout<=1'b1; cnt<=16'd0; end end s2:begin//主機輸出低電平延時19ms,結束后主機發出高電平 if(cnt >= 16'd19000)begin state <= s3; dout <= 1'b1; cnt <= 16'd0; end else begin cnt<= cnt + 1'b1; end end s3:begin//主機延時20-40us,結束后釋放數據總線,準備讀取數據 if(cnt>=16'd20)begin cnt<=16'd0; read_flag <= 1'b1; state <= s4; end else begin cnt <= cnt + 1'b1; end end s4:begin//等待從機響應 if(din == 1'b0)begin//從機響應 state<= s5; cnt <= 16'd0; end else begin cnt <= cnt + 1'b1; if(cnt >= 16'd65500)begin//超時自恢復 state <= s1; cnt<=16'd0; read_flag <= 1'b1; end end end s5:begin//檢查從機是否回應 if(din==1'b1)begin state <= s6; cnt<=16'd0; data_cnt <= 6'd0; end else begin cnt <= cnt + 1'b1; if(cnt >= 16'd65500)begin//超時自恢復 state <= s1; cnt<=16'd0; read_flag <= 1'b1; end end end s6:begin//等待第一個數據的起始信號點 if(din == 1'b0)begin//數據bit開始接收 state <= s7; cnt <= cnt + 1'b1; end else begin cnt <= cnt + 1'b1; if(cnt >= 16'd65500)begin//超時自恢復 state <= s1; cnt<=16'd0; read_flag <= 1'b1; end end end s7:begin// if(din == 1'b1)begin//決定數據的高電平起始點 state <= s8; cnt <= 16'd0; end else begin cnt <= cnt + 1'b1; if(cnt >= 16'd65500)begin//超時自恢復 state <= s1; cnt<=16'd0; read_flag <= 1'b1; end end end s8:begin//檢測高電平的時間,并判斷數據的 0 1 if(din == 1'b0)begin data_cnt <= data_cnt + 1'b1; state <= (data_cnt >= 6'd39)?s9:s7;//40bit數據接收完進入s9，否則進入s7繼續接收下一bit cnt<=16'd0; if(cnt >= 16'd60)begin data_buf<={data_buf[39:0],1'b1}; end else begin data_buf<={data_buf[39:0],1'b0}; end end else begin cnt <= cnt + 1'b1; if(cnt >= 16'd65500)begin//超時自恢復 state <= s1; cnt<=16'd0; read_flag <= 1'b1; end end end s9:begin//鎖存數據，并等待從機釋放總線 //data <= (data_buf[7:0] == (data_buf[15:8] + data_buf[23:16] + data_buf[31:24] + data_buf[39:32]))?data_buf : data; data <= data_buf; if(din == 1'b1)begin state <= s10; cnt<=16'd0; end else begin cnt <= cnt + 1'b1; if(cnt >= 16'd65500)begin//超時自恢復 state <= s1; cnt<=16'd0; read_flag <= 1'b1; end end end s10:begin//空一拍，產生完成一次讀數據的信號 state <= s1; cnt <= 16'd0; end default:begin state <= s1; cnt <= 16'd0; end endcase end end endmodule ``` 測試代碼 ``` module top2( input wire clk,//50MHz時鐘 //rst,// output reg led, //用于指示 input wire rxd, output wire txd, inout dht_io ); localparam DATA_NUM = 32; //*********************************PROCESS************************************** // 復位模塊 //****************************************************************************** wire clk_1mhz; //assign dht_io = (1'b1)?clk_1mhz:1'bz; reg rst_n ; reg [15:0]delay_cnt; always@(posedge clk) begin if(delay_cnt>=16'd35530)begin delay_cnt <= delay_cnt; rst_n <= 1'b1; end else begin rst_n <= 1'b0; delay_cnt <= delay_cnt + 1'b1; end end //指示燈 //assign txd = led; reg [31:0]cnt; reg start; reg led_f1,led_f2,tx_flag; always@(posedge clk) begin led_f1 <= led; //tx_flag <= led &(~led_f1); led_f2 <= led &(~led_f1); if(cnt >= 32'd25000000 - 1) begin cnt <= 0; led <=~led; end else begin cnt <= cnt + 1'b1 ; end if(cnt>=32'd12500000 - 1)start <=1'b1; else start <= 1'b0; end //-------------------------------------------- localparam s_s1=0; localparam s_s2=1; localparam s_s3=2; localparam s_s4=3; reg [DATA_NUM*8-1:0]my_data;//待發送的數據 reg [DATA_NUM*8-1:0]send_data_cache; reg [7:0]my_data_num;//發送的數據量 reg [7:0]send_data; reg to_uart_valid , to_uart_ready; reg [2:0]send_st; reg [7:0]data_cnt; always@(posedge clk) begin if(!rst_n)begin to_uart_ready <= 1'b0; to_uart_valid <= 1'b0; send_data <= 8'd0; send_st<= s_s1; data_cnt <= 8'd0; end else begin case(send_st) s_s1:begin//待機 if(tx_flag)begin send_st <= s_s2; to_uart_valid <= 1'b0; to_uart_ready<= 1'b0; data_cnt <= 8'd0; send_data_cache <= my_data<<((DATA_NUM - my_data_num)<<3); end else begin to_uart_valid <= 1'b0; to_uart_ready<= 1'b0; end end s_s2:begin if(data_cnt <= my_data_num-1'b1)begin to_uart_valid <= 1'b1; to_uart_ready <= (data_cnt >= my_data_num-1)?1'b0:1'b1; send_data <= send_data_cache[DATA_NUM*8-1:DATA_NUM*8 - 8]; send_data_cache<= send_data_cache << 8; data_cnt <= data_cnt + 1'b1; send_st <= (data_cnt >= my_data_num-1)?s_s3:s_s2; end end s_s3:begin to_uart_valid <= 1'b0; //to_uart_ready <= 1'b1; send_st <= s_s1; data_cnt<=8'd0; end default :send_st <= s_s1; endcase end end //----------------------測試模塊------------------------- myclock mclk_u1( .areset(!rst_n), .inclk0(clk), .c0(clk_1mhz), .locked() ); wire [39:0]dht_data; /* temp_dht11 u1( .clk(clk_1mhz), .nRST(~rst_n), .Data(dht_io), .data1(dht_data) );*/ wire done; DHT11 dht_inst1( .clk(clk_1mhz) , //1MHz時鐘 .start(start) ,//上升沿觸發采集 .rst_n(rst_n) , .dat_io(dht_io) , .data(dht_data) , .done(done) //.error ,//數據度錯誤時為1 //.done//完成一次轉換后數據更新 ); reg done_f1,done_f2,done_rising; always@(posedge clk) begin done_f1<=done; done_f2<=done_f1; done_rising <= done_f1 &(~done_f2); end //DHT11獲取數據 localparam s1 = 0; localparam s2 = 1; localparam s3 = 2; localparam s4 = 3; localparam s5 = 4; localparam s6 = 5; reg[4:0]st; reg [39:0]temp_data; always@(posedge clk) begin if(rst_n == 1'b0)begin my_data <= 128'd0; my_data_num <= 8'd0; tx_flag <= 1'b0; st <= s1; end else begin case(st) s1:begin//待機等待 if(done_rising)begin st<=s2; temp_data <= dht_data; end else begin st<=s1; tx_flag<=1'b0; end end s2:begin//數據校驗 if(temp_data[7:0] == temp_data[15:8]+temp_data[23:16]+temp_data[31:24]+temp_data[39:32])begin st<=s3; end else st<=s5; end s3:begin my_data[47:32] <= temp_data[39:24]; my_data[31:16] <= temp_data[23:8]; my_data[15:0] <="\r\n"; my_data_num <= 8'd6; tx_flag <= 1'b1; st <= s4; end s4:begin tx_flag<=1'b0; st<=s1; end s5:begin//錯誤 my_data <="數據錯誤\r\n"; my_data_num <= 8'd10; tx_flag <= 1'b1; st<=s4; end default:st<=s1; endcase end end //-----------------------end測試模塊--------------------- //獲取數據 //always@(posedge clk) //begin // if(rst_n == 1'b0)begin // my_data <= 128'd0; // my_data_num <= 8'd0; // tx_flag <= 1'b0; // end // else begin // if(led_f2)begin // tx_flag <= 1'b1; // my_data_num <= 8'd12; // my_data <= "我是袁洪平\r\n"; // end // else tx_flag<=1'b0; // end //end //串口模塊實例化 IP_UART u0 ( //.rs232_0_from_uart_ready (<connected-to-rs232_0_from_uart_ready>), // rs232_0_avalon_data_receive_source.ready //.rs232_0_from_uart_data (<connected-to-rs232_0_from_uart_data>), // .data //.rs232_0_from_uart_error (<connected-to-rs232_0_from_uart_error>), // .error //.rs232_0_from_uart_valid (<connected-to-rs232_0_from_uart_valid>), // .valid .rs232_0_to_uart_data (send_data), // rs232_0_avalon_data_transmit_sink.data .rs232_0_to_uart_error (), // .error .rs232_0_to_uart_valid (to_uart_valid), // .valid .rs232_0_to_uart_ready (to_uart_ready), // .ready .rs232_0_UART_RXD (rxd), // rs232_0_external_interface.RXD .rs232_0_UART_TXD (txd), // .TXD .clk_clk (clk), // clk.clk .reset_reset_n (rst_n) // reset.reset_n ); endmodule ```