# 可實現的運算  # 本次使用單精度浮點數除法器  testbeach文件： ```verilog `timescale 1ns / 1ps module tb( ); reg aclk ; reg w_valid; reg [31:0] a , b; wire s_axis_a_tready, s_axis_b_tready , y_valid; wire [31:0] y ; localparam N = 20; initial begin aclk = 0; forever aclk = #(N/2) ~aclk; end initial begin a=$random; b=$random; w_valid = 0; #N ; repeat( 100) @(posedge aclk) begin w_valid = 1; a = $random; b=$random; end end floating_point_0 u1 ( .aclk(aclk), .s_axis_a_tvalid( w_valid), //.s_axis_a_tready( s_axis_a_tready), .s_axis_a_tdata( a), // .s_axis_b_tvalid( w_valid), //.s_axis_b_tready( s_axis_b_tready), .s_axis_b_tdata( b), // .m_axis_result_tvalid( y_valid), //.m_axis_result_tready( ), .m_axis_result_tdata( y) ); endmodule ```