[TOC] ## 介紹 Yosys是Verilog RTL綜合的框架。它目前具有廣泛的Verilog-2005支持，并為各種應用程序領域提供了一組基本的綜合算法。所選功能和典型應用： * 處理幾乎所有可綜合的Verilog-2005設計 * 將Verilog轉換為BLIF / EDIF / BTOR / SMT-LIB /簡單的RTL Verilog /等等 * 內置的形式檢查屬性和等效性的方法 * 映射到ASIC標準單元庫（自由文件格式） * 映射到Xilinx 7系列和Lattice iCE40 FPGA * 自定義流程的基礎和/或前端 通過使用合成腳本組合現有過程（算法）并根據需要通過擴展Yosys C ++代碼庫添加其他過程，可以使Yosys適于執行任何綜合工作。 <br/> Yosys是根據ISC許可（與MIT許可或2子BSD許可類似的GPL兼容許可）許可的免費軟件。<br/> 事實上，yosys是一個解釋器，就如同python的解釋器一樣，于是從理論上我們可以在linux使用sheban來寫腳本運行！ [文檔推薦]([https://www.kutu66.com/GitHub/article\_94386](https://www.kutu66.com/GitHub/article_94386)) ## 在deepin上的安裝 **首先安裝所需要的依賴項目** ```bash sudo apt-get install build-essential clang bison flex \ libreadline-dev gawk tcl-dev libffi-dev git \ graphviz xdot pkg-config python3 libboost-system-dev \ libboost-python-dev libboost-filesystem-dev zlib1g-dev ``` **安裝yosys** 使用一下命令進行安裝 ```bash sudo apt-get install yosys ``` ## 關于幫助 對于不同版本的yosys，有些命令可能不同，yosys是一個解釋器，可以在終端輸入`yosys`進入，然后輸入`help`查看支持的命令！  ## 分步說明一個簡單的例子 **新建`foo.v`文件，文件內容如下所示** ``` module foo ( input a, input b, input c, output o ); assign o = (a & b) | c; endmodule ``` **終端切換到yosys解釋器，終端輸入yosys即可** ``` yosys ``` **讀入待分析的verilog文件** 當然根據版本的不同可能read要換成 read_verilog. ``` yosys> read -sv foo.v 1. Executing Verilog-2005 frontend. Parsing SystemVerilog input from `foo.v' to AST representation. Generating RTLIL representation for module `\foo'. Successfully finished Verilog frontend. ``` **指出頂層模塊** ``` yosys> hierarchy -top foo 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \foo 2.2. Analyzing design hierarchy.. Top module: \foo Removed 0 unused modules. ``` **將設計以Yosys的內部格式寫入控制臺** ``` yosys> write_ilang 3. Executing ILANG backend. Output filename: <stdout> # Generated by Yosys 0.8 (git sha1 5706e90) autoidx 3 attribute \top 1 attribute \src "foo.v:1" module \foo attribute \src "foo.v:8" wire $and$foo.v:8$1_Y attribute \src "foo.v:8" wire $or$foo.v:8$2_Y attribute \src "foo.v:2" wire input 1 \a attribute \src "foo.v:3" wire input 2 \b attribute \src "foo.v:4" wire input 3 \c attribute \src "foo.v:5" wire output 4 \o attribute \src "foo.v:8" cell $and $and$foo.v:8$1 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a connect \B \b connect \Y $and$foo.v:8$1_Y end attribute \src "foo.v:8" cell $or $or$foo.v:8$2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$foo.v:8$1_Y connect \B \c connect \Y $or$foo.v:8$2_Y end connect \o $or$foo.v:8$2_Y end ``` **將流程（always塊）轉換為網表元素并執行一些簡單的優化** ``` yosys> proc; opt 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.3. Executing PROC_INIT pass (extract init attributes). 4.4. Executing PROC_ARST pass (detect async resets in processes). 4.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 4.6. Executing PROC_DLATCH pass (convert process syncs to latches). 4.7. Executing PROC_DFF pass (convert process syncs to FFs). 4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \foo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \foo. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells. 5.6. Executing OPT_RMDFF pass (remove dff with constant values). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \foo.. removed 1 unused temporary wires. Removed 0 unused cells and 1 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). 5.9. Finished OPT passes. (There is nothing left to do.) ``` **使用xdot顯示設計網表** ``` yosys> show ``` 顯示結果如下：  同樣的實現，使用gv可用以下命令實現： ``` yosys> show -format ps -viewer gv ``` **將網表轉換為門邏輯并執行一些簡單的優化** ``` yosys> techmap; opt 7. Executing TECHMAP pass (map to technology primitives). 7.1. Executing Verilog-2005 frontend. Parsing Verilog input from `<techmap.v>' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. Mapping foo.$and$foo.v:8$1 ($and) with simplemap. Mapping foo.$or$foo.v:8$2 ($or) with simplemap. No more expansions possible. 8. Executing OPT pass (performing simple optimizations). 8.1. Executing OPT_EXPR pass (perform const folding). 8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells. 8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \foo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \foo. Performed a total of 0 changes. 8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells. 8.6. Executing OPT_RMDFF pass (remove dff with constant values). 8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \foo.. Removed 0 unused cells and 1 unused wires. 8.8. Executing OPT_EXPR pass (perform const folding). 8.9. Finished OPT passes. (There is nothing left to do.) ``` **將設計網表寫入新的Verilog文件** ``` yosys> write_verilog synth.v ``` 這樣流程基本就結束了！ ## 腳本方式執行 If ABC is enabled in the Yosys build configuration and a cell library is given in the liberty file `mycells.lib`, the following synthesis script will synthesize for the given cell library: ``` # read design read -sv foo.v hierarchy -top foo # the high-level stuff proc; fsm; opt; memory; opt # mapping to internal cell library techmap; opt # mapping flip-flops to mycells.lib dfflibmap -liberty mycells.lib # mapping logic to mycells.lib abc -liberty mycells.lib # cleanup clean ``` ## 簡單腳本實現 建立foo.ys文件，內容如下： ``` #!/usr/bin/env yosys read -sv foo.v hierarchy -top foo proc; opt; techmap; opt show write_verilog synth.v ``` 執行腳本可以使用 `yosys foo.ys`執行。<br/> 前面已經說到yosys是一個解釋器，那么我們可以為foo.ys添加執行權限，使用`chmod +x foo.ys`,然后就如同在linux上執行bash腳本一樣，使用 `./foo.ys`來執行。 ## yosys的web版本 我們有時候學習就只想很快的查看一些RTL或者GATE級的結果，安裝環境可能遇到各種問題，在這種情況下，我們可以使用yosys的web版本，鏈接地址： [yosys的web版本](http://hdl.huangzzk.info/)   ## 鏈接地址 [yosys github地址](https://github.com/YosysHQ/yosys) [測試源碼地址](https://gitee.com/yuan_hp/yosys-test)